The frequency synthesizer is commonly used in radio frequency devices to provide generation of local oscillator (LO) high frequency signals. Applications include, for example, the read channel in a hard disk drive, and for RF wireless communications such as cellular and digital cordless telephone local oscillator applications. Several of these applications require low phase noise and small frequency steps of the frequency synthesizer.
The read channel of a hard disk drive, for example, requires a synthesizer to generate clock frequencies of 180-500 MHz in 1 MHz steps for the timing recovery loop. The small frequency steps and wide output frequency range are required to adjust for the various data rates that hard disk manufacturers desire, with a phase noise low enough to have a >30 dB signal to noise ratio (S/N).
For an RF wireless application, a transmitter and receiver require a synthesizer to up convert and down convert modulated and received signals. In the RF wireless example, a clock frequency of 1100-1200 MHz in small 200 KHz steps is required of the synthesizer to meet the channel spacing requirements. Here again, low phase noise is required to have a high sensitivity in the receiver and not allow noise power to spill over into adjacent channels. In addition, the need is especially great in the RF wireless and other hand held portable device applications to integrate the entire synthesizer and VCO on a single semiconductor chip, for size, power, manufacturing, and economic reasons.
The phase locked loop (PLL) forms the basis of most modern carrier generation synthesizer solutions. The synthesizer technique aims to get a high quality (low phase noise), high frequency oscillator to be locked to a stable, low level, low cost (often crystal derived) source.
Two important factors affecting the design of a carrier frequency source are frequency stability and phase noise. Frequency stability generally refers to the stability of the oscillator with respect to temperature and aging, and determines the channel spacing required to contain the modulated carrier signal. Conversely, for a given regulated channel spacing, the frequency stability determines the maximum data rate that can be supported without violating the channel boundary. Phase noise generally refers to the oscillator phase jitter resulting in a broadband component to the carrier signal which will extend into adjacent channels. If the phase noise is too high, this can corrupt the modulation source itself, and limit adjacent channel selectivity due to reciprocal mixing.
FIG. 1 illustrates the effect of reciprocal mixing to produce phase noise with a non-ideal oscillator. FIG. 1 shows a plot 100 of signal strength about a center carrier frequency fC (110), with a wanted channel region 120. Phase jitter in the oscillator frequency results in a component of the signal strength, identified by the plot region 130, in the adjacent channel region 140, creating phase noise as the channels mix.
A simple form of PLL synthesizer contains a voltage controlled oscillator (VCO) operating at the required carrier frequency, a frequency divider, which is a digital divider circuit, a phase detector circuit and a loop filter. FIG. 2 illustrates this type of simple conventional synthesizer 200. The synthesizer circuit 200 acts to lock the reference frequency (fREF) to fVCO/N, resulting in an output frequency (carrier) of N·fREF. The input reference frequency fREF is compared in a phase detector 220 to that of the divided down feedback from the output of a divider 245, as a result of the frequency produced by a VCO 240. The output of the phase detector 220 is filtered by a loop filter 230, which produces a voltage to control the VCO 240 frequency output N·fREF.
FIG. 3 illustrates a conventional single loop synthesizer circuit 250. By adding a further divider NR (255) to the synthesizer of FIG. 2, between the reference frequency source and the PLL, it is possible to synthesize a whole range of output frequencies with value: n·fREF/nR. With the addition of a divide by nM prescaler 290, to the PLL circuit 250, an even wider range of output frequencies fSYNTH may be synthesized with value: nM·n·fREF/nR.
FIG. 4 illustrates an exemplary synthesizer spectrum of signal strength vs. frequency. The plot 150 of the typical synthesizer spectrum has a center carrier frequency fC (160), with a loop bandwidth 170, formed by the VCO spectrum 180, the reference source spectrum 190, and the multiplied reference noise floor 195 (e.g., divide by N, 245 of FIG. 2).
Previous solutions, as shown in FIG. 3, for hard disk drive applications use a single PLL to generate the desired output frequency. To meet the small frequency step size, the reference frequency must be low, the multiplication factor must be high, and the loop bandwidth must be narrow. To meet the phase noise requirements however, the reference frequency must be high, the multiplication factor must be low, and the loop bandwidth must be wide. These conflicting requirements associated with frequency step size and phase noise limit the performance that can be obtained with a single PLL.
In one prior art solution, a two loop PLL uses a fine tune loop as a reference for a second loop that does a coarse frequency tuning. This technique, however, creates another problem, as the multiplication factor of the coarse tune loop multiplies the fine tune loop frequency step size, and therefore, increases the phase noise out of the fine tune loop, disadvantageously increases the reference sidebands, and makes full integration of the entire circuit on a single chip more difficult.
A more recent extension of the basic PLL based synthesizer is the fractional-N device. A fractional-N loop with a dual modulus prescaler can be used for a read channel to improve phase noise and frequency resolution. But, increasingly finer frequency resolution causes spurious signals to appear inside the loop bandwidth. For example, a 20 MHz reference signal with a loop bandwidth of 1 MHz can use a 0.25 fractional part without significant problems because the 5 MHz sideband caused by the fractional process is far enough beyond the loop bandwidth to get rejected. This results in a 5 MHz step size resolution, but does not reach the exemplary goal of 1 MHz frequency resolution or lower, as mentioned above.
For wireless applications, the phase noise requirement is so low that an external VCO is required in a fractional-N synthesizer. A fractional divide by N PLL is used to get small frequency steps, and a narrow bandwidth is used to filter out the spurious signals generated by the method. The fractional divide by N also puts spurious signals inside the loop bandwidth and sigma delta techniques are used in an attempt to eliminate the effects of the fractional spurs. Consequently, the fractional N technique has limited improvement usefulness.
Another conventional multi-loop synthesizer has a fine and coarse tune loop solution which uses a single sideband (SSB) mixer to combine the two signals produced. The prior art use of the SSB mixer is much more complicated and adds more mixing products that get multiplied by the N in the final PLL. The SSB mixer implementation has relatively high noise, high sidebands, narrow bandwidth, and may require 0 and 90 degree outputs from the VCO, which restricts the design possibilities.
Theoretically, a mixer will perform the mathematical multiplication of the two input signals, creating components positioned at frequencies equal to the sum and difference of the input signals and no additional components. For this to be the case, however, the mixing (multiplying) device must be perfectly linear and there must be no leakage on the input signals to the output port.
The term “balanced” in the double balanced mixer implies that neither of the input terms will appear at the mixer output. In practice, suppression of these input components is never perfect in an analog mixer circuit, (it may be virtually perfect in a digital implementation). A balanced mixer can be implemented using a transformer coupled diode arrangement (termed a passive mixer, which is however, not practical to implement on integrated circuit chips) or using an active transistor based design, the most well known of which is known as the Gilbert cell mixer.
FIG. 5 illustrates a typical CMOS Gilbert cell mixer circuit. The Gilbert cell mixer 300 of FIG. 5 mixes low frequency inputs (LO+/−) at 310, and RF frequency inputs (RF+/−) at 320 to produce an intermediate frequency output (IF+/−). The Gilbert cell mixer includes a balanced complimentary pair of (e.g., MOSFET) transistors at each input of the lower frequency LO inputs and the higher frequency RF inputs, to minimize the effect of any differential offset currents.
FIG. 6 illustrates the response of the signal strength vs. frequency of a non-ideal mixer. The plot 330 of FIG. 6 indicates the components of the input modulation frequency (fm) 340 and the carrier frequency (fc) 350, and the mixer sum (fc+fm) 370/375 and difference (fc−fm) 380/385 products at the odd harmonics of the carrier frequency (fc) 350 and (3fc) 390. Several of the common mixers produce signals at odd harmonics of the carrier frequency, particularly the diode ring mixer. Fortunately, the harmonics are easily filtered out by the low pass filter (LPF) used in the synthesizer PLL.
Thus, conventional synthesizer single loop systems have conflicting requirements which limit noise, step size and bandwidth performance for the applications considered. Conventional multi-loop synthesizers either produce an undesirable step size, increase the phase noise, or increase the sidebands.
Prior art use of an SSB mixer adds complicated circuitry, more mixing products, and multi-phase signals to be generated.
A fractional divide by N synthesizer can produce small frequency steps, but usually requires an external VCO because of the phase noise, and a narrow bandwidth filter for the spurious signals generated inside the loop bandwidth to eliminate the effects of the fractional spurs.
In addition, there is a need in the RF wireless and other hand held portable device applications to integrate the entire synthesizer and VCO on a single semiconductor chip, for size, power, manufacturing, and economic reasons.
Accordingly, there is a need for a synthesizer circuit for generating a high frequency in small frequency steps with low phase noise, in a small, low power solution, which is fully integrated on a semiconductor chip.